Numerous applications such as portable power supplies, amplifiers, EEPROMs, charge pumps on-chip, etc., need to be operated at higher voltage levels. These extended voltages typically range between 12V and 20V. In order to keep costs down is desirable to be able to use base 5V technology to build these high voltage devices, thereby avoiding having to resort to special high voltage technologies.
One solution that makes use of only existing masks and thereby limits costs is the extended drain device, also sometimes referred to as lateral DMOS (LDMOS), illustrated in FIG. 1. The device 100 includes a source 102 formed in an n-well 104, and a drain 106 formed in an n-well 108. In order to accommodate the higher voltage levels the drain 106 is extended in length as shown in FIG. 1. Due to the high voltage applied to the drain 106 a high voltage junction is formed between the p-well 110 under the gate polysilicon 112, and the n-well 108. As a result, the gate polysilicon requires a thick field oxide 120, e.g., a shallow trench isolation region or LOCOS region to provide a reduced surface field (RESURF). Furthermore, the high junction voltage together with the large size of the drain 106 results in a large depletion region in the n-well 108 under the field oxide 120. This depletion region is a critical part of the device since the electric field distribution in this region determines not only the breakdown voltage but also impacts the hot carrier degradation (HCD) of the device. The field oxide traps injected charge carriers, thus resulting in HCD. Thus the design of the extended drain part becomes a complex issue to avoid irregularities and achieve the desired voltage breakdown and drain-source resistance parameters.